As is known, conventional Field-Effect Transistors (FETs) comprise one transport channel, which is generally induced by the application of a gate voltage above a threshold value. It has one source and one drain. Although a FET may have one or more gates, typically there is only one top gate which is formed above the transport channel having an appropriate thin gate insulator layer. Additionally, Field-Effect Transistors (FETs) having a back gate have also been reported. Moreover, there are also FIN-FETs where the gate region surrounds the semiconductor. All of these structures have the common characteristic that there is one channel which is connected to one drain. When used in logic circuits, conventional FETs are limited and are typically used to process one bit of information at a time. For example, in complementary metal oxide semiconductor (CMOS) inverters (a NOT logic gate), there is one input and one output. The input is connected to the gate which is formed by electrically connecting the gates of an n-channel FET and a p-channel FET and the logic output is connected to the drain regions of both transistors which are also electrically connected. As such, when an input is high (e.g. logic state “1”) the output is low (e.g. logic state “0”).